The field of the invention relates to semiconductor manufacturing lithography technology and more specifically to mask features designed to improve critical dimension control.
The various conducting lines and other features found within a semiconductor chip are created by lithographic means. That is, light is passed through a mask and focused onto a semiconductor wafer surface coated with a resist. The mask contains opaque and transparent areas such that, for negative resists, opaque regions correspond to the desired features formed on the semiconductor wafer surface (such as transistor gates or metal interconnection lines). Alternatively, if a positive resist is used, the transparent regions correspond to the desired features.
The critical dimension of a semiconductor process is used to refer to one of the process""s smallest achievable dimensions. For example, the smallest feature size formed in a direction parallel to the surface of the wafer. Currently, a horizontal critical dimension of leading edge semiconductor devices is 0.13-0.25 micron (xcexcm). As the projection optics of today""s leading edge exposure tools reduce the optical image from the mask by approximately 4:1, the critical dimension of today""s leading edge masks is approximately 0.52-1.0 xcexcm (4xc3x970.13-0.25=0.52-1.0).
A problem with masks is the variation of the mask""s critical dimension at the outer edge of a die pattern. That is, as shown in FIG. 1, a mask 100 typically has a central area 101 having the various features formed on the semiconductor die. This central area 101 is also referred to as a die pattern, an active area, an active device area or the like. The area outside the active device area, referred to as the inactive area 102, is largely unused space. For the most part, the most meaningful features on the mask are those that help create the features on the silicon chip (which are within the active area 101). Typically, alignment features 103a-d (used for mask alignment purposes) are the main features used within the inactive area 102.
It has been observed that the smallest achievable feature size (i.e., a critical dimension) on the mask increases at the outer edge 104 of the active area 101. For example, FIG. 2a shows the variation 200 of a mask""s Final Check Critical Dimension (FCCD) with the mask""s radius. Toward the outer edge of the active area 201 (approximately 55000 xcexcm from the mask""s center in this example) there is a sharp increase in the critical dimension range from approximately 0.910-0.940 xcexcm to 0.950-0.965 xcexcm.
This lack of control usually affects features commonly referred to as metro cells. Metro cells 202 are a set of features used for the alignment of a lithographic stepper. As metro cells are usually placed near the outer edge of the active area 104 (referring briefly back to FIG. 1), metro cells 202 tend to be more distorted than other features. Thus FIG. 2a shows the critical dimension of the metro cells 202 within an undesired 0.950-0.965 xcexcm critical dimension range. FIG. 2b shows an SEM photograph of an inner feature edge 203 that is within a mask""s active device area (101 of FIG. 1) and sufficiently far from the active device area edge (104 of FIG. 1). FIG. 2c shows an SEM photograph of a metro cell edge 204 from the same mask as that shown in FIG. 2b. The loss of critical dimension control is seen by comparison of FIG. 2b with FIG. 2c. The metro cell""s edge 204, being substantially more sloped than the inner feature edge 203, results in a larger metro cell 202 critical dimension.
The inability to keep the metro cell""s critical dimension within a normal range (e.g., 0.910-0.940 xcexcm) results in manufacturing inefficiencies. Specifically, the mask has to be manually or custom exposed in order to compensate for the distortion to the metro cell. This custom fitting procedure slows down the manufacturing process resulting in added expense (through wasted time). If the metro cell critical dimension could be manufactured within the same range as the features within the active area, the custom fitting procedure may be eliminated resulting in substantial savings to current manufacturing costs.
An apparatus is described comprising a mask having an active device area and a moat. The moat substantially surrounds the mask active device area and has a width greater than a plasma specie diffusional length. A method is described comprising depositing a layer of resist on a mask substrate having transparent and opaque layers; and then exposing the resist layer to radiation. The radiation is patterned to produce features within an active device area. The radiation is also patterned to produce a moat substantially surrounding the active device area having a width greater than a plasma specie diffusional length.